This invention relates integrated circuits, and, more particularly, to a method and system for controlling the slew rate of a signal applied to a transmission line using open drain technology to minimize inductive voltage transients internal to packaged devices and minimize other voltage asperties coupled to the transmission line.
As the operating speed of electronic systems, such as computer systems and memory devices, continue to increase, the speed at which digital signals must be coupled continues to increase. As a practical matter, the speed at which a digital signal may be coupled through a signal line is reduced if the signal is reflected from various nodes in the signal line, such as connections to the signal line by various electronic circuits. Reflection of digital signals may be avoided by coupling the digital signals through a transmission line having an impedance matched to the impedance of circuitry coupled to the line. Electronic circuits can be designed to be impedance matched to a transmission line in this manner if the number of electronic circuits coupled to the line and the impedance of such circuits remains fixed. However, it is common to vary the number of electronic circuits coupled to a signal lines. For example, in computer systems, the number of memory modules coupled to a memory controller through a data bus, address bus, and control bus may vary. If these buses are impedance matched to the memory modules when the computer system is initially placed in service, the buses may not be impedance matched when additional memory modules are coupled to the buses.
One conventional approach to allowing a varying number of electronic devices to be coupled to a transmission line while maintaining impedance matching between the devices and the line is through open drain technology. The principle of open drain technology can be explained with reference to FIG. 1. As shown in FIG. 1, a memory controller 10 generating a binary signal is coupled to one end of a transmission line 14. An opposite end of the transmission line 14 is coupled to a voltage source 16 through a terminating resistor 18. For purposes of illustration, the voltage of the voltage source 16 is assumed to be 1.5 volts, although it may be any voltage in practice. The resistance of the terminating resistor 18 is substantially the same as the characteristic impedance Z0 of the transmission line 14. For purposes of illustration, the characteristic impedance Z0 of the transmission line 14 and the resistance of the resistor 18 is assumed to be 20 ohms. The signal generated by the memory controller 10 is a switched current signal that switches between two values of current. For example, one binary value may be represented by a current of 0 ma., and the other binary value may be represented by a current of 25 ma. Under these circumstances, a voltage V0 at a node 20 to which the transmission line 14 is coupled will switch between 1.5 volts when the current is 0, and 1.0 volt when the current is 25 ma. The voltage V0 at the node 20 thus switches between two levels to represent respective binary values. Also coupled to the transmission line 14 at a plurality of respective nodes 22a,b . . . n are memory devices 24a,b . . . n , which also output a switched current signal.
Although the voltage at the nodes 20 and 22a,b . . . n switch between two values, the effect of doing so by varying the current between two values is significantly different from simply using a switched voltage source to drive the voltage applied to the nodes 20 and 22a,b . . . n between two values. If, for example, the memory device 24b outputs a switched voltage signal on the transmission line 14, the signal will propagate through the transmission line 14 away from the memory device 24b in both directions. When the signal reaches the memory controller 10, it will be reflected from node 20 because of the impedance mismatch between the 25 ohm characteristic impedance of the transmission line 14 and the high impedance at the input to the inactive memory controller 10. By the time the reflected signal reaches the memory device 24a, the memory device 24a may be outputting a signal. If the memory device 24a was outputting a switched voltage signal, the voltage at the node 22a would remain constant despite the reflected signal reaching the node 22a because the memory device 24a would draw or provide sufficient current to maintain the voltage substantially constant. The magnitude of an impedance from an A.C. or transient point of view is proportional to the ratio of the change in voltage to the change in current. Consequently, the input impedance of the memory device 24a resulting from a small change in voltage and a large change in current is relatively small. The low impedance of the memory device 24a would cause further reflection of signal from the node 22a. Furthermore, the impedance at each node 22a,b . . . n would change greatly depending upon whether a memory device 24a,b . . . n was coupled to the node 22a,b . . . n. 
If a signal was reflected from the memory controller 10 and the memory device 24a was outputting a current switched signal, the effect would be substantially different. In such case, the voltage at the node 22a would change responsive to the reflected signal reaching the node 22a because the memory device 24a maintains the current substantially constant. Consequently, the input impedance of the memory device 24a resulting from a relatively large change in voltage and a very small change in current is relatively large. In fact, the impedance of the memory device 24a may be so large that the memory device 24a has no effect on the signal reflected from the memory controller 10. Under these circumstances, the memory device 24a does not even electrically appear to be coupled to the transmission line 14. The memory devices 24a,b . . . n can therefore be added or removed to the transmission line 14 without altering the performance of the transmission line 14.
In practice, the memory controller 10 and the memory devices 24 are able to drive the transmission line 14 with a switched current signal through a drain of a MOSFET transistor (not shown) that is xe2x80x9copenxe2x80x9d or unconnected to any other circuitry. The advantages of using this open drain technology are not entirely without some countervailing disadvantages. One disadvantage is the switching of current supplied or drawn by an open drain device generally results in a corresponding change in the power supply current drawn by the device. This change in current drawn by the device through inductive power supply lines (not shown) can produce voltage transients on the power supply lines that result in power supply noise. Such power supply noise can adversely affect the operation of other circuitry in the open drain device as well as other devices that are coupled to the same power source.
The magnitude of a voltage transient is proportional to the inductance of a power supply line through which the current is drawn and the first derivative of the current through the line as a function of time. Thus, reducing the rate of current change, i.e., the first derivative of the current, reduces the magnitude of the voltage transients generated in a power supply line. One approach to reducing the rate of current change in an open drain device will be explained with reference to FIGS. 2 and 3. As shown in FIG. 2, an open drain device outputs a switched current signal I that changes from I0 to I1 and then subsequently back to I0. The switched current signal I results in a voltage E that changes correspondingly from E0 to E1 and then subsequently back to E0. As also shown in FIG. 2, the first derivative Ixe2x80x2 of the current signal I is a positive pulse coincident with the leading edge of the switched current signal and a negative pulse coincident with the falling edge of the switched current signal.
The peak magnitude of the first derivative Ixe2x80x2 of the current signal I can be reduced using a conventional technique that will be explained with reference to FIG. 3. As shown in FIG. 3, instead of using a single open drain transistor or several open drain transistors switched at the same time, several open drain transistors may be switched at two different times. As a result, the switched current signal I is composed of two switched current signals I1, I2 each of which transitions at a different time. Each of these switched current signals I1, I2 generates a respective voltage (not shown) and a respective first derivative I1xe2x80x2, I2xe2x80x2 of the switched current signals I1, I2. However, since the magnitude of each individual switched voltage signal I1, I2, is relatively small, so also is the magnitude of each individual first derivative signal I1xe2x80x2, I2xe2x80x2. As a result, the peak value of each of the first derivative signals I1xe2x80x2, I2xe2x80x2 is approximately one-half the magnitude of the first derivative signal Ixe2x80x2 shown in FIG. 2.
One conventional circuit for applying a switched current signal to a bus is shown in FIGS. 4 and 5. The circuit will be explained in the context of a memory device, although it will be understood that it may be used with other types of devices. With reference to FIG. 4, a delay circuit 100 receives a clock signal TCLKL and outputs a delayed clock signal TCL after a predetermined delay. Similarly, a delay circuit 102 receives a clock signal TCLKLB and outputs a delayed clock signal TCLB after a predetermined delay. The relative phases of the TCLKL, TCL, TCLKLB and TCLB signals are shown in FIG. 6. As shown in FIG. 6, TCLKL and TCLKB are compliments of each other, and TCL and TCLB are delayed versions of TCLKL and TCLKLB, respectively. The TCLKL signal is initially low and the TCKLB signal is initially high so pass gate 114 is conductive. As a result the MUXI signal corresponds to the level of the READE (i.e., read even) signal from an even data path. In contrast, the READO signal is from an odd data path. When the TCLKL signal subsequently transitions high and the TCLKLB signal transitions low, the pass gate 104 becomes conductive and the pass gate 114 becomes non-conductive, this making the MUXI signal equal to the level of the READO signal. Thus, the MUXI signal is alternately equal to the READE and READO signals. The READE and READO signals are received at either a half data rate (i.e., on every fourth clock transition) or full data rate (i.e., on every other clock transistor), thus making the MUXI signal valid at the full data rate or a double data rate (i.e., every clock transition).
The MUXI signal is applied to the input of an inverter 110. For purposes of explanation, assume the MUXI signal is initially low. The output of the inverter 110 is thus initially high, and it subsequently transitions low. The high-to-low transition at the output of the inverter 110 causes the output of an inverter 120 to transition from low to high. The low at the output of the inverter 110 also turns ON two PMOS transistors 124, 126 that couple the output of the inverter 120 to a supply voltage to assist in the low-to-high transition at the output of the inverter 120. Parascitic capacitance represented by a capacitor 128 has the effect of slightly smoothing transitions at the output of the inverter 120. The resulting signal Q is used by the circuitry shown in FIG. 5, as explained below.
A second pair of pass gates, 130, 132, inverters 134, 136, PMOS transistors 140, 142 and capacitor 146 are interconnected and operate in the same manner as described above with respect to the pass gates, 104, 114, inverters 110, 120, PMOS transistors 124, 126 and capacitor 128 except the pass gates 130, 132 are controlled by the delayed TCL and TCLB signals. As a result, a QL signal is generated from the READE and READO signals at a slightly later time than the Q signal is generated. The resulting signal QL is also used by the circuitry shown in FIG. 5.
With reference to FIG. 5, a driver circuit 140 includes 11 current branch circuits 144a-k coupled in parallel to each other. Each of the branch circuits 144 includes a respective current regulating NMOS transistor 150a-k and a respective switching NMOS transistor 152a-k. The current regulating transistors 150a-k preferably have binary weighted channel widths so that the channel width of each transistor 150 is twice as wide as the channel width of the adjacent transistor 150. Thus, for example, the channel width of the transistor 150c is twice as wide as the channel width of the transistor 150b, and the channel width of the transistor 150d is twice as wide as the channel width of the transistor 150c, etc. The transistors 150a-k are selectively controlled by suitable control signals CNTL less than 0:10 greater than  that are generated by conventional means to select the current draw. The magnitudes of these CNTL less than 0:10 greater than  are typically ground potential or a voltage that is sufficiently low to provide a high drain-to-source impedence for the transistors 150a-K. The switching transistors 152a-g are controlled by the Q signal generated by the circuitry shown in FIG. 4, as previously explained. The switching transistors 152h-k are controlled by the QL signal generated by the circuitry shown in FIG. 4.
As explained above, the Q and QL signals have slightly different phases, thereby producing a switched current signal of the type shown in FIG. 3 composed of two different switched current components switching at different times. Even though the circuitry shown in FIGS. 4 and 5 reduces power supply noise resulting from the switched current signal, it nevertheless produces a degree of power supply noise that can be excessive in some applications. The peak magnitude of the power supply noise could be reduced by increasing the number of differently phased, switched current components used to produce the switched current signal. However, doing so might make the width of the switched current signal excessive and thereby limit the operating speed of memory devices using such open drain technology.
There is therefore a need for an open drain driver circuit and method that can further reduce the magnitude of induced power supply noise without limiting the operating speed of electronic devices using open drain technology.
An open drain driver circuit and method applies switched current signals to an output terminal responsive to a digital input signal applied to an input terminal. The open drain driver circuit includes a switch control circuit receiving a digital signal at the input terminal. The switch control circuit generates a plurality of switching signals each of which transitions between first and second voltage levels. Significantly, the rate at which at least one of the transitions occurs in a plurality of the switching signals is controlled in at least two phases. The open drain driver circuit also includes a current control circuit coupled to receive the switching signals. The current control circuit is structured to provide the switched current signals at the output terminal having a first magnitude responsive to the switching signals being at the first voltage level and having a second magnitude responsive to the switching signals being at the second voltage level. By controlling the rate at which at least one of the transitions occurs, the rate of change of the current corresponding to the switched current signals can be limited to minimize power supply noise.